FSM Design

Project Description 50 Word Description Functional Description Scoring Algorithm Pin Count Pin Map Interactive Floor Plan Old Block Diagrams Timing Diagrams FSM Timing Diagram Input Timing Diagram Logic Timing Diagram Output Timing Diagram FSM Design and MEG FSM State Table FSM Inputs and Outputs FSM Magic Layout FSM IRSIM Major Blocks & Subcells Logic Diagram Links Cell Hierarchy Magic and IRSIM Performance Analysis IRSIM Spice Summary About Us Mid-Semester Status Report

FSM State Table FSM Inputs and Outputs FSM Magic Diagram FSM IRSIM FSM MEG --MEG program --Finite State Machine for Mastermind Project --state transition on every clock INPUTS: S2 S1 S0 RESTART enterG enterK GC2 GC1 GC0; OUTPUTS: latchG shift0 shift1 shift2 shift3 latchGBS resetV latchVBS latchK WLK1 WLK0 latchGC resetGC incrementGC latchLS latchB resetBW latchW resetO latchO latchC; RESET ON RESTART TO A; A: IF enterK THEN B(resetO resetGC latchK) ELSE LOOP; B: GOTO C(resetBW); C: IF enterG THEN D(latchG incrementGC latchGC shift0 latchGBS resetV) ELSE LOOP; D: GOTO E(latchC shift1 latchVBS latchGBS); E: GOTO F(latchB latchC shift2 latchGBS latchVBS); F: CASE (S0 S1 S2) 0 0 1 => K(latchO); ENDCASE => G(latchW latchC shift3 latchGBS latchVBS); G: GOTO H(latchW latchC); H: GOTO I(latchW); I: CASE (GC0 GC1 GC2) 1 1 1 => J(latchO); ENDCASE => B(latchO); J: GOTO A(WLK0); K: GOTO A(WLK1 WLK0 latchLS); FSM State Diagram