JAWs Logic Diagram

17 November 1998

17 November 1998
Changed "4Imm" to "FourImm".

Added ClearRegs comment at bottom.

15 November 1998

Changed IF signals to InF and the second MemRead (the MUX control) to Mem2Reg.

Added a latch clocked on CLKB after the add1 unit.

Added a latch clocked on CLKA in the path from the Branch mux to the PC.

Changed the PC latch to qualified B.

Changed the IF latch to qualified A.

Changed the SetRM latch to qualified A.

Instead of the PC control being Branch+InF, we need to add some more logic.

• Take the branch signal, send it into a new latch clocked on CLKA.
• We have a new control signal, SetPC. Send it into a new latch clocked on CLKA.
• OR the outputs of these latches. The qualified A version of this signal is the control for the PC latch.

06 November 1998

After memory, IF latch now qualified on CLKB.

05 November 1998

Latches added before and after ALU, after data read from memory, before PC adder. Mux added before MemReg, and MemReg combined to one latch. Clock labels and qualified signals denoted when applicable.

11 October 1998

Instruction and data memory combined to one "Memory" unit, a more accurate reflection of the external memory. "IF" control signal determines input with mux, and latches the instruction output. Input as memory address is 9 bits, 8 are the desired address and the 9th determines instruction or data memory.

Bus width labels added.

Branch AND changed to NAND; branch mux labels swapped. Branch logic clarified ("=0?" and ">0?" labels).

PC addder changed from 2 to 1.

05 October 1998

Branch logic added - no longer depends on ALU result.

Added WriteZero control signal for ZERO instruction.

22 September 1998

Original submitted.